This article reviews the pros and cons of the SSD controller in "Enable data cache and Disable data cache" and looks into their approaches and application scope. Please note that "cache" here refers to ones for buffering before writing in NAND Flash rather than for the "read hit rate."
As shown in figure 1, an SSD controller is composed of three sections: front, buffer and back. In general, the front side is designed to hand shake with the host and in processing certain standard commands. The buffer side is aimed at buffering the read/write data in SRAM/DRAM buffer, while the back takes care of Flash commands and correcting the data bit errors with the ECC engine.
A typical approach adopted by the current SSD controller is saving data from the host in the data buffer first and then writing them in NAND Flash with hardware DMA engine enabled by firmware once the volume in the buffers hit a certain threshold. This is called "Data cache mode" and enjoys the following merits:
1. Combine into one program page: NAND Flash mandates programing one page at one time. The page size most commonly adopted is 16K bytes. For a write command with 4K bytes data it's more efficient to buffer 4 “chunks” of 4K bytes data in the Data Cache to write in NAND.
2. Write data over the same LBA (Logical Block Address: for write-in data of the LBAs) directly when write-data contains the same LBAS to reduce SSD WAI (Write Amplification). This is especially helpful in the case of DRAM Cache.
The Data cache mode comes with a big shortfall in case of power outages. When outages occur, data buffered in data cache, which most likely would be SRAM or DRAM, may be lost or severely damaged. This has to be addressed for applications than cannot risk data loss.
One of the ways to address it is to add a super CAP in the SSD to give it enough power for data in the data cache to get updated in the NAND Flash in case of power outages. This, quite evidently, entails added costs. The bigger the cache, the larger capacity capacitor is required to have more time for data refreshing.
The other option is the "Non-cache mode." As shown in the figure above, data is written into NAND Flash directly through data caching instead of buffering there. The controller sends a message "command ready" to the host only when the write-in command of NAND Flash is ready. This approach does not raise costs and only requires changes with PCBs as no extra super CAP is needed. Its disadvantages are equivalently clear: it is not very efficient as every command can only reply to the host after the NAND data write-in operation has ended. On the other hand, when write-in of the host is smaller than the least unit of NAND write-in, some dummy patterns have to be padded which raises the WAI of SSD and decreases total data volume that can be written into the SSD.
Each of these three approaches comes with their own pros and cons as described above. In some quasi-industrial control applications (e.g. POS), every outage is abnormal as the host does not have any normal power shutdown process, yet data loss remains something that has to be prevented. However, applications like this require few data write-ins and are less demanding in performance and total write-in volume. The non-cache mode may be an appropriate option here.