When data is transmitted from one device to another, certain problems may arise, such as signal attenuation, noise interference, etc.; as a result, End-to-End (E2E) Data Path Protection has emerged to ensure that accessed and retrieved data are correct as well as to avoid errors during data storage.
E2E Data Path Protection is a feature of Solid-State Drives. It can expand the range of error detection. Its coverage ranges from the entire path of computer systems, hard drives, and data transmissions and functions to verify data correctness.
SSD End-to-End Data Path Protection
Each SSD contains one controller that is responsible for the communication between the SSD and the host system. No matter which specifications (such as 2.5-inch, mSATA, M.2, etc.) or which communication protocols (such as SATA or NVMe), all of them will be written or read through the SSD controller.
When data is read or written, its path will access different sites. The writing path accesses the sites through Host--> PCIe IP -->Data Buffer-->Flash IP-->NAND Flash, while the reading path accesses the sites in a reverse manner.
E2E Data Path Protection mainly ensures that data can be protected during transmission. If the controller's internal RAM moves data and a Soft Error occurs, the system can also detect errors and avoid erroneous data transmission to the host side. In short, the main purpose of E2E Data Protection is to ensure that each site maintains independent debugging capabilities and avoids the generation of erroneous data during transmission.
Error Detection and Correction
In order to ensure data is transmitted from the SSD controller to a NAND storage device while maintaining integrity, the SSD controller incorporates "bug fix" technology (called "Error Correction Code" (ECC)) to detect and remediate most errors that may affect data on the track. NAND Flash chips incorporating other error correction information and written data to each chunk allows the SSD controller to simultaneously correct errors while reading data chunks. In addition, bit errors can occur during normal NAND operation; but such errors can also be corrected in real time by ECC.
However, in extremely rare cases, data errors cannot be corrected upon reading data chunks. At this time, the SSD controller will classify the scenario as "Unable Error Correction Code" (UECC) and return to the host computer.
ADATA SSD also integrate backup blocks for NAND Flash devices. These spare blocks are typically located in the OP space of the hard drive, and users cannot access or retrieve them. If a NAND device has too many errors in the data block, the block will be marked as an "error chunk" and replaced. Therefore, the use of "spare chunks" can prolong the lifespan and durability of SSDs.
